Omkar Bhilare Omkar Bhilare ¹

Abstract—I design Coarse-Grained Reconfigurable Array (CGRA) architectures and build the CAD algorithms that map applications onto them, aiming for near-ASIC efficiency without giving up programmability.

Index Terms—CGRA architecture, reconfigurable computing, CAD algorithms, computer architecture, RTL design and verification, HLS.

Introduction

I am a PhD candidate at the University of Toronto, working with Prof. Jason Anderson. My research centers on Coarse-Grained Reconfigurable Arrays (CGRAs), a class of reconfigurable architectures that approach ASIC performance and energy efficiency while staying programmable at runtime. I design and explore CGRA architectures [1], [2], and build the CAD mapping algorithms that run applications on them [3]. I also completed a research internship at RIKEN Center for Computational Science with Dr. Kentaro Sano [2].

Before my PhD, I was a Silicon Design Engineer at AMD in India. As an undergraduate in Electronics, I interned with Prof. Paolo Ienne at EPFL on Dynamatic, with Prof. Kamakoti at IIT Madras on the Shakti processor, and took part in Google Summer of Code with BeagleBoard.org on BeagleWire. My undergraduate thesis accelerated deepfake detection on FPGAs [4].

I am open to collaborations in computer architecture, reconfigurable computing, and RTL design & verification. If you would like to collaborate, reach out to me at omkar.bhilare@mail.utoronto.ca.