Omkar Bhilare
PhD student · Computer Architecture · Reconfigurable Computing
I am a PhD student at the University of Toronto, working with Prof. Jason Anderson. My research centers on Coarse-Grained Reconfigurable Arrays (CGRAs), a class of reconfigurable architectures that approach ASIC performance and energy efficiency while staying programmable at runtime. I design and explore CGRA architectures, and build the CAD mapping algorithms that run applications on them. I also completed a research internship at RIKEN Center for Computational Science with Dr. Kentaro Sano.
Before my PhD, I was a Silicon Design Engineer at AMD in India. As an undergraduate in Electronics, I interned with Prof. Paolo Ienne at EPFL on Dynamatic, with Prof. Kamakoti at IIT Madras on the Shakti processor, and took part in Google Summer of Code with BeagleBoard.org on BeagleWire.
I am open to collaborations in computer architecture, reconfigurable computing, and RTL design & verification. Feel free to reach out.
Publications
bibtex
@inproceedings{ide2026hwsharing,
author = {Ide, R. and Ahmed, T. and Adhi, B. and Kawai, S. and Bhilare, Omkar and Anderson, Jason H.},
title = {Hardware Sharing for Area Optimization of Floating-Point {ALUs}},
booktitle = {Highly Efficient Accelerators and Reconfigurable Technologies (HEART)},
year = {2026},
doi = {10.1145/3814576.3814584}
}
CGRA4HPCA '26
Extends an elastic CGRA and the CGRA-ME 2.0 CAD flow with partial and full predication, comparing a local-predicate design against a dedicated 1-bit global predicate network.
bibtex
@inproceedings{bhilare2026predication,
author = {Bhilare, Omkar and Ragheb, Omar and Adhi, Boma and Sano, Kentaro and Anderson, Jason and Ueno, Tomohiro},
title = {Predication in Elastic {CGRAs}},
booktitle = {Workshop on CGRAs for High Performance Computing (CGRA4HPCA) at IPDPS},
year = {2026},
url = {https://ieeexplore.ieee.org/document/11652038}
}
HEART '24
Partitions and places applications across sixteen 4x4 CGRAs connected by a 2D mesh network-on-chip, and studies the quality and runtime of the CAD flow.
bibtex
@inproceedings{wei2024noc,
author = {Wei, Haron and Bhilare, Omkar and Waqar, Hamas and Anderson, Jason},
title = {{CAD} Techniques for {NoC}-Connected Multi-{CGRA} Systems},
booktitle = {Highly Efficient Accelerators and Reconfigurable Technologies (HEART)},
year = {2024},
doi = {10.1145/3665283.3665297}
}
PDCAT '23
Accelerates a quantized MesoNet / EFF-YNet deepfake detector on the Versal VCK5000, reaching 316.8 FPS at 93% accuracy.
bibtex
@inproceedings{bhilare2023deepfake,
author = {Bhilare, Omkar and Singh, Rahul and Paranjape, Vedant and Chittupalli, Sravan and Suratkar, Shraddha and Kazi, Faruk},
title = {{DEEPFAKE CLI}: Accelerated Deepfake Detection Using {FPGAs}},
booktitle = {Parallel and Distributed Computing, Applications and Technologies},
publisher = {Springer Nature Switzerland},
pages = {45--56},
year = {2023},
doi = {10.1007/978-3-031-29927-8_4}
}
Invited Talks
- March 2026 “Adaptive Data Compression on CGRAs” 2nd Research Meeting on Adaptive Bandwidth Compression Hardware (ABC-HW '26), Tohoku University, Sendai, Japan (remote)
News
- Feb 2026 Predication in Elastic CGRAs
- Jun 2024 Paper accepted at HEART 2024
- Dec 2023 2023 Fall Work Presentation
- Apr 2022 Received a sample Arty A7-35T for PipelineC Project
- Jan 2022 Got Accepted in the Summer EPFL Program @ LAP Lab
Projects
Hardware and FPGA projects, mostly from my undergraduate years.
RISC-V Core
Designed and Verified a RV32I core.
VGA driver
Made a VGA Driver for Tang primer FPGA
8 bit computer
Designed a 8-bit Computer using SAP logic
ESP32 Dev Board
ESP32 Dev Board for Embedded and Robotics Application
7-segment driver
Made a Seven Segment Driver for Tang primer FPGA
Aqua Farm Monitor
Transferred Sensors Data between Two ESP32s on LORA WAN
PONG on FPGA
Running a Famous PONG game on BeagleWire FPGA
Universal IC
Universal IC which can emulate All ICs from 74 family.
8-Bit ALU
8 Bit ALU implementation on Altera Cyclone II